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Abstract
A new 美国留学生电子科技论文 controller architecture for image stable displays is described which enables lower system hardware cost and complexity, easier access to ultra-low and zero power states, and expanded flexibility in panel resolution, signal timing, and operating mode. This architecture is contrasted with currently available EPD controllers, and a specific implementation of the approach with 8 bits of storage per screen pixel is examined infuse with two example EPD panels.

1.Background
Over the last few years, AMLCDs have become pervasive in mobile electronics devices thanks to their superior performance and appearance over previously used passive matrix solutions. One result of this has been inclusion of AMLCDinterfacing circuitry into SOC chips targeted at mobile devices and the appearance of highly integrated display related ICsdesigned to directly attach to active matrix panels. Electronic system designers and engineers have also become intimately familiar with the interface and operation of AMLCDs as a result of this progression.

In parallel with this trend, new display technologies exhibiting instability or image stability such as EPDs have become increasingly capable of addressing mainstream commercial applications. When used on an active matrix backplane and incorporated into a system, these displays have different needs than an AMLCD of similar resolution and capability.

Bias voltages and driver supply rails are somewhat different, and these needs are met by the power hardware design. In addition, many bitable displays also have specialized requirements at the data level to produce the waveforms required by the imaging material on the panel. For example, since microencapsulated electrophoresis displays need only be driven when a change in pixel state is requested, simultaneous access is required to the current image as well as the next image to determine if a pixel is changing, and if so what the precise nature of the change will be. Typically a specific waveform is developed for each type of pixel state change and must be applied to the requisite pixels based on the current and next image information. This takes the form of a lookup table indexed by current pixel value, next pixel value, and frame index.

The core logic function of a controller for image stable displays of this type is to apply the correct waveform to each pixel in the display to effect its transition from current to next image. Previous commercial controllers like that used in the Sony Liberian the E Ink AM-100 evaluation kit [2] have used a video cordlike approach, with the new image being sent to the display controller subsystem over a memory style interface and stored in local SRAM along with the current image. For an update, the display controller itself reads the two images from SRAM, lookup the waveform from flash, and generates driver timing signals to scan the panel and execute the update. A block diagram of this type of controller, as used in the AM-100 developer kit system is shown in Figure 1.

Because the interactive interfacing, pixel calculations, memory addressing, and scan generation are fairly complicated, the controller logic had to be implemented in an ASIC in order to reduce cost and physical size enough to make volume production reasonable prospect. The necessity of including three separate memory chips along with the complex core l本论文由英语论文网提供整理，提供论文代写，英语论文代写，代写论文，代写英语论文，代写留学生论文，代写英文论文，留学生论文代写相关核心关键词搜索。