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Abstract
In 澳洲留学生液晶面板科技研究论文 this paper, we present the newly developed intra-panel interface targeting to replace conventional multi-drop bus architecture with point-to-point differential interface. The multilevel signaling scheme is adopted to remove separate clock and control signal lines by embedding clock information into multilevel signal. The clock embedding scheme removes the skew problem found in previously announced intra-panel interface, and provides lower EMI. The simple multi-level signal detector is used to regenerate the clock signal from the data stream and does not require any sophisticated clock recovery unit in the receiver. Therapy can be an effective solution to large size TFT LCDapplications due to the reduced signal lines, lower EMI, and lower power consumption.

1.Introduction
As the LCD TV market matures, the trends of LCD panels are going towards larger sizes and higher resolutions. That trend requires not only the increased data rate but also the challenging requirements such as cinema-quality visual performance, low electro-magnetic interference (EMI) and low power consumption. However, the conventional intra-panel interfaces which are designed for the LCD monitors cannot fulfill those requirements.
Sooner or later, the adoption of the new intra panel interface is inevitable. As an approach to solve these problems some researchers supposed new interfaces. Some of them adopted new configurations such as point-to-point configuration [1] and cascading structure [2] to reduce the signal lines. As a new solution for the tougher and challenging LCD system, we have developed a new intra panel interface standard, Apia (AdvancedIntra Panel Interface). In this paper, we will present the introduction of the newly developed Apia which needs only one pair of signal lines between timing controller and a column driver and the obtained results applied to 32” WXGA/768p (1366X768) resolution TFT LCD panel.

2. Advanced Intra-panel Interface
2.1 Apia Architecture
Figure 1 illustrates the overall configuration of Apia. Compared with multi-drop bus architecture, Apia uses a point-to-point interface architecture to achieve the high data rate and reduced number of signals. The elimination of visa and stubs as well as the good impedance matching characteristics in PCB trace enables us to get the signals with fine quality. The number of signal lines can dramatically reduced because it depends on the number of column driver not on the RGB color depth. Even though it exploits less number of signal lines, the required bandwidth is not increased much because every channel operates simultaneously.

6. References
[1] R. I. McCartney, et al, A Third Generation Timing Controller And Column Driver Architecture Using Point-to-Point Differential Signaling, SID Symposium Digest, 60-1, 2004
[2] I. K. Chang, et al, A New Interface WiseBusTM for Large LCD TV Applications, SID Symposium Digest, 57.2, 2005
[3] B. H. Berkeley, et al, Invited Paper: World’s First ABSI LCD Module, SID Symposium Digest, 57.1, 2005
[4] R. I. McCartney, et al, www.51lunwen.org/australiathesis/ Evaluation Results of LCD Panels using the PPDSTM Architecture, SID Symposium Digest, 57.3, 2005